Semiconductor integrated circuit and power-supply control method

ABSTRACT

A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.

CROSS REFERENCES TO RELATED APPLICATIONS

The present application is a reissue application of application Ser. No.12/318,934, now U.S. Pat. No. 7,956,677, issued Jun. 7, 2011. Thepresent invention contains subject matter related Japanese PatentApplication JP 2008-006955 filed in the Japan Patent Office on Jan. 16,2008, the entire contents of which being incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit forcontrolling a transition of a plurality of switch transistors, which areused for supplying power to a plurality of circuit cells and cutting offthe supply of power to the circuit cells, from a turned-off state to aturned-on state and relates to a power-supply control method forcontrolling such a transition.

2. Description of the Related Art

A MTCMOS (Multi-threshold Complementary Metal Oxide Semiconductor)technology is known as a technology for controlling switch transistors,which are used for supplying power to a circuit and cutting of thesupply of power to the circuit.

The threshold voltage of a transistor employed in a logic circuit or thelike is a typical design value. In general, it is necessary to reducethe threshold voltage so that no signal delay is generated due to adecreased power-supply voltage and/or a miniaturized device. If thethreshold voltage of a transistor employed in a logic circuit or thelike is small, a leak current flowing through the transistor is large.In accordance with the MTCMOS technology, a transistor as a power-supplyswitch is designed to have a large threshold voltage for a circuit in astopped state in comparison with a transistor employed in a logiccircuit or the like and is used for breaking a leak current path of thelogic circuit or the like in order to prevent its power from beingconsumed wastefully.

In an application of the MTCMOS technology to a circuit block, localvoltage lines referred to as the so-called virtual VDD line and theso-called virtual GND line are provided locally in the circuit block.The local voltage lines are each connected to a real voltage line and areal reference-voltage line respectively through a switch transistor forsupplying power to the circuit block and cutting off the supply of powerto the circuit block. Referred to as a real VDD line and a real VSS linerespectively, the real voltage line and the real reference-voltage lineare common global voltage lines outside the circuit block.

A switch transistor is provided between the real VDD line and afunctional circuit which is started and stopped repeatedly. As analternative, a switch transistor is provided between the real VSS lineand such a functional circuit. As another alternative, a switchtransistor is provided between the real VDD line and such a functionalcircuit whereas a switch transistor is provided between the real VSSline and the functional circuit. Normally, the switch transistorprovided between the real VDD line and a functional circuit is ap-channel metal oxide semiconductor (PMOS) transistor whereas a switchtransistor provided between the real VSS line and a functional circuitis an n-channel metal oxide semiconductor (NMOS) transistor.

Operations to activate and stop a functional circuit included in anMTCMOS applied block are controlled by a circuit included in anon-MTCMOS applied block which receives power from the real VDD line andthe real VSS line, entering an operating state at normal times, after asemiconductor integrated circuit has been activated. The non-MTCMOSapplied block also includes the switch control circuit which controlsoperations to turn on and off the switch transistor for supplying powerto circuit cells and cutting off the supply of power to the cells. Inaddition to the switch conduction control circuit, the non-MTCMOSapplied block also include circuits, such as a clock generation circuitand another repeater buffer, used mainly for controlling the entireintegrated circuit (IC) and storing data representing input/outputsignals.

If the stopped time of the functional circuit in the MTCMOS appliedblock is long, it is quite within the bounds of possibility that thelocal voltage line such as the virtual VSS line is electrically chargedwith a leak current flowing from another internal circuit and raised toa high electric potential close to the real VDD line. Thus, when apower-supply cutting-off switch transistor is turned on at the time thefunctional circuit in the MTCMOS applied block is reactivated,electrical discharging of the virtual VSS line causes an accidentalcurrent to flow to the real VSS line. This accidental current isreferred to as, for example, a rush current. As the rush current flowsto the real VDD line, the current becomes a positive noise potential andpropagates to a non-MTCMOS applied block adjacent to the MTCMOS appliedblock.

A phenomenon similar to that described above may occurs on the real VDDline. Since the accidental current flows from the real VDD line, anegative noise potential appears, which drops the potential on the realVDD line abruptly.

In either case, these noise voltages caused by power-supply noisespropagate to circuits operating in an adjacent circuit block and cause asteep decrease of the power-supply voltage amplitude, giving rise to adelay effect such as generation of an operation delay as a result. Thecircuits operating in an adjacent circuit block include a clockgenerator circuit and/or a repeater buffer.

As a countermeasure against the power-supply noises, Philippe Royannezetc., “90 nm Low Leakage SoC Design Technique for Wireless Application,”2005 IEEE International Solid-State Circuits Conference, DIGEST OFTECHNICAL PAPERS, P138 (referred to as non-patent document 1), forexample, discloses a technology according to which a plurality of PMOSswitch transistors are connected in parallel between the global real VDDline and the local virtual VDD line and control signals each applied tothe gate of one of the transistors are each delayed in order togradually reduce the impedance of connection between the global real VDDline and the local virtual VDD line.

SUMMARY OF THE INVENTION

In accordance with the technology disclosed in non-patent document 1,however, even though the peak of the power-supply noises can berepressed, the technology has long time to execute the control.

A semiconductor integrated circuit according to an embodiment of thepresent invention includes: a first voltage line on which a specific oneof a power-supply voltage and a reference voltage appears; a secondvoltage line; a plurality of circuit cells each receiving powergenerated as a difference between a voltage appearing on the secondvoltage line and the other one of the power-supply voltage and thereference voltage; and a plurality of switch transistors connected inparallel between the first and second voltage lines to serve as switchtransistors including switch transistors having conducting-stateresistances which are different from each other. The circuit furtherincludes a switch conduction control section configured to control atransition of each of the switch transistors from a non-conducting stateto a conducting state at separate points of time while abiding by a rulestating: “Any specific one of the switch transistors shall be put in aconducting state only after all the switch transistors each having aconducting-state resistance greater than the conducting-state resistanceof the specific switch transistor have been put in a conducting state.”

It is possible to provide the embodiment of the present invention with adesirable configuration in which each of the switch transistors employsa plurality of unit transistors which are controlled by the switchconduction control section to be turned on or turned off at the sametime and have a uniform conducting-state resistance.

As an alternative, it is possible to provide the embodiment of thepresent invention with another desirable configuration in which, whencontrolling a transition of each of the switch transistors from anon-conducting state to a conducting state at separate points of time,the switch conduction control section fixes the number of the switchtransistors to be controlled at the same point of time for each of thepoints of time.

As another alternative, it is possible to provide the embodiment of thepresent invention with a further desirable configuration in which, whencontrolling a transition of each of the switch transistors from anon-conducting state to a conducting state at separate points of time,the switch conduction control section gradually increases the number ofthe switch transistors to be controlled at the same point of time.

It is also possible to provide the embodiment of the present inventionwith a still further desirable configuration in which, when controllinga transition of each of the switch transistors from a non-conductingstate to a conducting state at separate points of time, the switchconduction control section gradually decreases time intervals ofconduction controls.

A semiconductor integrated circuit according to another embodiment ofthe present invention includes: a first voltage line on which a specificone of a power-supply voltage and a reference voltage appears; a secondvoltage line; a plurality of circuit cells each receiving powergenerated as a difference between a voltage appearing on the secondvoltage line and the other one of the power-supply voltage and thereference voltage; a plurality of switch transistors connected inparallel between the first and second voltage lines; and a switchconduction control section configured to control a transition of each ofthe switch transistors from a non-conducting state to a conducting stateat a plurality of time intervals of conduction controls including atleast a specific time interval shorter than a preceding time interval.

A power-supply control method implemented by an embodiment of thepresent invention to serve as a power-supply control method to beadopted by a semiconductor integrated circuit. The circuit includes: afirst voltage line on which a specific one of a power-supply voltage anda reference voltage appears; a second voltage line; a plurality ofswitch transistors connected in parallel between the first and secondvoltage lines to serve as switch transistors including switchtransistors having conducting-state resistances which are different fromeach other; and a plurality of circuit cells each receiving powergenerated as a difference between a voltage appearing on the secondvoltage line and the other one of the power-supply voltage and thereference voltage. The power-supply control method is adopted by thesemiconductor integrated circuit for controlling an operation to supplypower to the circuit cells by putting each of the switch transistors ina turned-off state or a turned-on state through a conduction control ofa transition of each of the switch transistors from a non-conductingstate to a conducting state at separate points of time while abiding bya rule stating: “Any specific one of the switch transistors shall be putin a conducting state only after all the switch transistors each havinga conducting-state resistance greater than the conducting-stateresistance of the specific switch transistor have been put in aconducting state.”

It is possible to provide the semiconductor integrated circuit adoptingthe power-supply control method according to the embodiment with adesirable configuration in which: each of the switch transistors isconfigured to include a plurality of unit transistors having uniformconducting-state resistances, controlled through the conduction controlto be turned off and turned on at the same point of time; and during theconduction control, the number of the unit transistors to be controlledsimultaneously at the same point of time is made gradually greater.

In accordance with the configuration described above, when the circuitcells are recovered from a stopped state to enter an operating state forexample, the switch conduction control section controls the switchtransistors to make a transition from the turned-off state to theturned-on state.

To put it in detail, the switch conduction control section controls eachof the switch transistors from a conducting state to a non-conductingstate by turning on the switch transistors at separate points of timewhile abiding by a rule stating: “Any specific one of the switchtransistors shall be put in a conducting state only after all the switchtransistors each having a conducting-state resistance greater than theconducting-state resistance of the specific switch transistor have beenput in a conducting state.”

As described above, a switch transistor or a plurality of unittransistors are controlled to enter the conducting state or thenon-conducting state at the same time. In a first switch conductioncontrol operation, a switch transistor having a relatively largeconducting-state resistance is put in a conducting state. Thereafter, atleast one switch conduction control operation is carried out in order toput the other one or plurality of switch transistors in a conductingstate at the same time. In the execution of the first and subsequentswitch conduction control operations, in accordance with the ruledescribed above, switch transistors each has different aconducting-state resistance are properly and sequentially selected andput in a turned-on state.

The rule stating: “Any specific one of the switch transistors shall beput in a conducting state only after all the switch transistors eachhaving a conducting-state resistance greater than the conducting-stateresistance of the specific switch transistor have been put in aconducting state” is a rule to be applied to switch conduction controloperations carried out on switch transistors having conducting-stateresistances which are different from each other and is not a rule to beapplied to switch conduction control operations carried out on switchtransistors having conducting-state resistances which are equal to eachother. It is thus allowable to put switch transistors havingconducting-state resistances which are equal to each other in aturned-on state consecutively in two or more switch conduction controloperations carried out successively.

Where the switch conduction control is executed to put switchtransistors in a turned-on state sequentially one transistor afteranother and there are two or more switch transistors havingconducting-state resistances which are equal to each other, first ofall, the switch conduction control is executed to put switch transistorsincluded in a group as switch transistors having large conducting-stateresistances in a turned-on state in an arbitrary order, then, the switchconduction control is executed to put switch transistors included in agroup as switch transistors having small conducting-state resistances ina turned-on state in an order abiding by the rule. In this way, anyspecific switch transistor having small conducting-state resistance isput in a turned-on state on condition that all the switch transistorseach having a conducting-state resistance greater than theconducting-state resistance of the specific switch transistor have beenput in a turned-on state.

Each time a conduction control operation is carried out, the resistancebetween the first and second voltage lines is reduced gradually. Thedecrease in such resistance increases gradually in the course of theentire conduction control even though some times of consecutivedecreases are generated.

When a particular current flows through a particular switch transistorput in a turned-on state as a result of carrying out a conductioncontrol operation, the difference in voltage between the first andsecond voltage lines decreases so that, when at least one nextconduction control operation is carried out in order to put the nextswitch transistor having the uniform (or smaller) value ofconducting-state resistance in a turned-on state, the magnitude of a newcurrent flowing through the next switch transistor is smaller than themagnitude of the particular current. In the course of the entireconduction control, however, the aforementioned decrease in resistancebetween the first and second voltage lines increases gradually so thatthe current flows easily in comparison with a configuration in whichdecreases in such resistance are uniform. As a result, the higher-levelvoltage of the two voltages appearing on the first and second voltagelines quickly approaches the lower-level voltage of the two voltages.

In accordance with the other embodiment, in order to carry out a voltageequalization process at a high speed in the same way, the switchconduction control section controls a transition of each of the switchtransistors from a turned-off state to a turned-on state by turning onthe switch transistors at a plurality of switch turning-on timeintervals including at least a specific switch turning-on time intervalshorter than a switch turning-on time interval preceding the specificswitch turning-on time interval.

Typically, the larger the difference in voltage between the first andsecond voltage lines in initial switch conduction control, the longerthe switch turning-on time interval between a switch conduction controloperation carried out to put a switch transistor in a turned-on stateand a next switch conduction control operation carried out to putanother switch transistor in a turned-on state. That is to say, theswitch conduction control section controls a transition of each of theswitch transistors from a non-conducting state to a conducting state byturning on the switch transistors at a plurality of switch turning-ontime intervals so that, in the course of the entire switch conductioncontrol, the switch turning-on time interval is gradually shortened.

In either of the embodiments, in initial conduction control for a largedifference in voltage between the first and second voltage lines, someof switch transistors are each controlled to enter a conducting state sothat the resistance between the first and second voltage lines does notabruptly decrease. Thus, the maximum magnitude of a current flowingthrough the first voltage line is small. As a result, it is possible torepress the peak of variations of a voltage appearing on the firstvoltage line. In addition, in comparison with control to sequentiallyput switch transistors having a uniform conducting-state resistance atequal turning-on time intervals, the fast voltage equalization processdescribed above reduces the length of time it takes to complete theconduction control operations which are commenced at the start of theswitch conduction control.

Each of the embodiments described above executes conduction control onswitch transistors connected in parallel between a first voltage lineand a second voltage line by gradually increasing the number ofaforementioned switch transistors each put in a conductive state. (Thetransistors having the uniform conducting-state resistance are allowedto be turned on consecutively.) Thus, each of the embodiments offers amerit that it is possible to reduce the length of time it takes tocomplete a sequence of conduction control operations which are commencedat the start of the switch conduction control while repressing the peakof variations of a voltage appearing on the first voltage line, that is,repressing the peak of power-supply noises.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a first typical overall configurationof a semiconductor integrated circuit according to an embodiment of thepresent invention;

FIG. 2A is a diagram showing a typical internal layout of a circuit cellincluding a switch transistor SWT;

FIG. 2B is a diagram showing a typical internal layout of anothercircuit cell including a switch transistor SWT and a logic circuitsection 5;

FIG. 3 is a diagram showing a typical array of aforementioned circuitcell shown in FIG. 2A, in the first typical overall configuration shownin FIG. 1;

FIG. 4 is a block diagram showing a second typical overall configurationof a semiconductor integrated circuit according to the embodiment of thepresent invention;

FIG. 5 is a diagram showing the locations of the real power-supply linepair and the switch transistors in the second typical overallconfiguration shown in FIG. 4;

FIGS. 6A and 6B are explanatory diagrams showing a first basic conceptof a switch control in the embodiment;

FIGS. 7A and 7B are explanatory diagrams showing a second basic conceptof the switch control in the embodiment;

FIG. 8 is an explanatory diagram of a typical example of the switchcontrol in the embodiment;

FIGS. 9A and 9B are model diagrams each shows a relation between avoltage appearing on a first voltage line and the lapse of time of thetypical example of the switch control;

FIG. 9C is a waveform diagram showing activate-timing charts of controllines; and

FIG. 10 is an explanatory diagram of the other example of the switchcontrol in the embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT First Typical OverallConfiguration

FIG. 1 is a block diagram showing a first typical overall configurationof a semiconductor integrated circuit according to an embodiment of thepresent invention.

In the configuration shown in FIG. 1, a plurality of input/output cells40 are arranged to form an array along each of the four sides of arectangular semiconductor chip in which the semiconductor integratedcircuit is created. In a chip area surrounded by the input/output cells40, a real VDD line 2D and a real VSS line 2S are provided as firstvoltage lines. To put it in detail, the real-voltage line pairs (2D, 2S)are oriented in the horizontal (row) direction and the vertical (column)direction so as to form a voltage line layout having the shape of alattice. In addition, the real-voltage line pairs (2D, 2S) surround eachlattice square, forming the external lattice frame of the latticesquare. The external lattice frame of a lattice square serves as anumber of power-supply points for the lattice square.

The real-voltage line pairs (2D, 2S) oriented in the horizontal (row)direction are created from a metal layer different from a metal layerfor creating the real-voltage line pairs (2D, 2S) oriented in thevertical (column) direction, and the metal layers form a multi-layerline structure. In this structure, the real VDD lines 2D and the realVSS lines 2S may cross each other in a state of being electricallyinsulated from each other.

Each of the lattice squares surrounded by the real-voltage line pairs(2D, 2S) and its external lattice frame form a segment of the chip area.In this segmented and relatively large chip area, a non-MTCMOS appliedblock (hereinafter referred to as non-applied circuit block) 30 isprovided. In the various sizes of segmented chip areas, a number ofMTCMOS applied blocks (hereinafter referred to as MTCMOS circuit blocks)are provided. That is to say, each of circuit blocks other than thenon-applied circuit block 30 is an MTCMOS circuit block. In the diagramof FIG. 1, one of the MTCMOS circuit blocks is denoted by referencenumeral 1.

It is to be noted that, in the diagram of FIG. 1, each of the MTCMOScircuit block 1 and the remaining MTCMOS circuit blocks is connected tothe real-voltage line pairs (2D, 2S). On the other hand, the diagram ofFIG. 1 shows as if the non-applied circuit block 30 were not connectedto the real-voltage line pairs (2D, 2S). In actuality, however, thenon-applied circuit block 30 is also connected to the real-voltage linepairs (2D, 2S).

The MTCMOS circuit block 1 includes a plurality of switch transistors.The switch transistors are each provided in an area not occupied bycircuit cells each used for implementing a function of the MTCMOScircuit block 1. As an alternative, each of the switch transistors isprovided as a circuit cell. If the switch transistor is provided as acircuit cell, the circuit cell may or may not include logic circuitsother than the switch transistors. That is to say, the circuit cell mayinclude only the switch transistor.

FIGS. 2A and 2B are diagrams each showing a typical internal layout of acircuit cell including a switch transistor. To be more specific, in FIG.2A, a circuit cell 4A includes a switch transistor SWT as only one ofactive element whereas a circuit cell 4B includes a switch transistorSWT and a logic circuit section 5 in FIG. 2B.

It is to be noted that, in each of the diagrams of FIGS. 2A and 2B, theswitch transistor SWT for controlling the operation to supply and cutoff a reference voltage VSS is an NMOS transistor. As shown in each ofthe diagrams of FIGS. 2A and 2B, each of the circuit cells includescircuit-cell elements which are a branch line 20S, a branch line 20D anda virtual VSS line 30S. The branch line 20S is referred to as a part ofthe first voltage line whereas the virtual VSS line 30S is referred toas a second voltage line as described below. A reference voltage VSS isasserted on the branch line 20S whereas a power-supply voltage VDD isasserted on the branch line 20D.

Included in the MTCMOS circuit block 1, the branch line 20S is a branchoriginated from the real VSS line 2S shown in the diagram FIG. 1. Alsoincluded in the MTCMOS circuit block 1, the branch line 20D is a branchoriginated from the real VDD line 2D shown in the diagram FIG. 1 in thesame way as the branch line 20S.

On the other hand, the virtual VSS line 30S is peculiar to the MTCMOScircuit block 1. That is to say, the virtual VSS line 30S is providedonly inside the MTCMOS circuit block 1. Referred to as the secondvoltage line, the virtual VSS line 30S performs the role to supply thereference voltage VSS to a logic circuit 5 and other circuits in thecircuit cell.

As shown in FIG. 2B, the switch transistor SWT is provided on the sideof the reference voltage VSS, that is, between the virtual VSS line 30Sas the second voltage line and the branch line 20S as the first voltageline as described above. However, the wiring of the switch transistorSWT is by no means limited to this configuration. For example, theswitch transistor SWT can also be provided on the side of thepower-supply voltage VDD. In this case, a virtual VDD line (not shown)as the second voltage line for supplying the power-supply voltage VDD tothe logic circuit 5 can be newly provided between the branch line 20D asa first voltage line and the logic circuit 5 whereas a PMOS transistoris provided between the virtual VDD line and the branch line 20D toserve as the switch transistor. As an alternative, the switchtransistors can be provided both sides of the reference voltage VSS andthe power-supply voltage VDD.

In order to make the explanation easy to understand, in the followingdescription, it is assumed that the switch transistor SWT is providedonly to the side of the reference voltage VSS.

As shown in FIGS. 2A and 2B, the switch transistor SWT is connectedbetween the branch line 20S and the virtual VSS line 30S, and the logiccircuit 5 is connected between the branch line 20D and the virtual VSSline 30S.

It is to be noted that elements inside the circuit cell are connected toeach other by properly placing the circuit cell. That is to say, it isnot always necessary to create wires for connecting the elements to eachother. The circuit cells are connected to each other by making use ofwires on an upper layer.

The switch transistor SWT is connected to a control line CL on the upperlayer.

Typically, as many control lines CL as switch transistors SWT areprovided for the MTCMOS circuit block 1. As an alternative, one controlline CL is provided for a predetermined plurality of switch transistorsSWT.

The control line CL is connected to a switch control section 31 servingas the switch conduction control section employed in the non-appliedcircuit block 30 shown in the diagram of FIG. 1 to serve as the switchconduction control section mentioned before. The switch control section31 controls an operation to put the switch transistor SWT in a turned-on(conducting) state or a turned-off (non-conducting) state through thecontrol line CL. Since the switch control section 31 is employed in thenon-applied circuit block 30, the switch control section 31 receives thepower-supply voltage VDD and the reference voltage VSS to operate atnormal times after the semiconductor integrated circuit in question isactivated.

FIG. 3 is a diagram showing a typical array of aforementioned circuitcells 4A each shown in FIG. 2A.

In the typical array shown in FIG. 3, seven circuit cells 4A each shownin the diagram of FIG. 2A are arranged in the column direction. An areain which the circuit cells 4A are arranged is referred to as a switchlayout area 1A.

In the diagram of FIG. 3, a circuit cell 4C includes the logic circuit5, the branch line 20S, the branch line 20D and the virtual VSS line30S. Thus, the circuit cell 4C is a circuit cell obtained as a result ofremoving the switch transistor SWT and the control line CL from thecircuit cell 4B shown in FIG. 2B. The circuit cells 4C are arranged inthe row direction to form a cell line on a row. FIG. 3 shows seven celllines each provided on a row.

Two adjacent cell lines provided on two rows separated away from eachother in the column direction perpendicular to the row direction share abranch line 20S and a branch line 20D.

On the upper layer of a multi-layer wiring structure of the circuitcells 4A in the switch layout area 1A, on the other hand, up to sevencontrol lines CL1 to CLn as well as the real VDD line 2D and the realVSS line 2S which are shown in the diagram of FIG. 1 are laid out bywell utilizing the multi-layer wiring structure.

It is to be noted that the layout of the switch transistors SWT does nothave to be oriented in the column direction shown in FIG. 3. Forexample, the layout of the switch transistors SWT can be oriented in therow direction. In this case, circuit cells 4A shown in the diagram ofFIG. 2A or circuit cells 4B shown in the diagram of FIG. 2B are laid outin the row direction so that the layout of the switch transistors SWT isoriented in the row direction automatically. Then, a plurality ofaforementioned control lines CL each connected to the gate electrode ofone of the switch transistors SWT are oriented in the row or columndirection.

Second Typical Overall Configuration

FIG. 4 is a block diagram showing a second typical overall configurationof the semiconductor integrated circuit according to the embodiment ofthe present invention.

In the configuration shown in FIG. 4, a plurality of input/output cells40 are arranged to form an array along each of the four sides of arectangular semiconductor chip in which the semiconductor integratedcircuit is created. In a chip area surrounded by the input/output cells40, a real VDD line 2D and a real VSS line 2S which are not shown in theblock diagram of FIG. 4 are provided to form a real-voltage line pairserving as first voltage lines. To put it in detail, each of thereal-voltage line pairs (2D, 2S) is a pair of parallel real power supplylines 2D and 2S oriented in the horizontal (row) direction and thevertical (column) direction so as to form a voltage line layout havingthe shape of a lattice.

In the chip area of the circuit layout shown in FIG. 4, some circuitblocks are provided. In the typical configuration shown in the blockdiagram of FIG. 4, a circuit block 32 referred to as a conduction areais provided in the chip area. The circuit block 32 has basic componentsof a semiconductor integrated circuit. The basic components include aCPU, a register, a memory and a power-supply circuit. The circuit block32 corresponds to the non-applied circuit block 30 in FIG. 1. Thecircuit block 32 receives the power-supply voltage VDD and the referencevoltage VSS to operate at normal times after the semiconductorintegrated circuit including the circuit block 32 is activated.

In addition to the circuit block 32, in the chip area of the circuitlayout shown in FIG. 4, a number of circuit blocks each referred to as amacro are provided. Each of the macro circuit blocks has a function of alogic circuit useful for the semiconductor integrated circuit.

The macro circuit blocks are classified into two large categories, i.e.,non-applied circuit blocks 33 and MTCMOS circuit blocks 1. Much like thecircuit block 32, each of the non-applied circuit blocks 33 receives thepower-supply voltage VDD and the reference voltage VSS to operate atnormal times after the semiconductor integrated circuit including themacro circuit blocks is activated. In the typical configuration shown inthe block diagram of FIG. 4, each of the non-applied circuit blocks 33is referred to as a conductive macro whereas each of the MTCMOS circuitblocks 1 is referred to as a power-supply blocking macro. As describedbefore, a non-applied circuit block is a circuit block to which theMTCMOS technology is not applied.

FIG. 5 is a diagram showing the locations of the real power-supply linepair (2D, 2S) and the switch transistors SWT in the MTCMOS circuit block1.

In FIG. 5, reference numeral 1B denotes a functional circuit cell layoutarea (hereinafter referred to as cell layout area) of the MTCMOS circuitblock 1. For example, in the cell layout area 1B, circuit cells eachobtained as a result of removing the switch transistor SWT and thecontrol line CL from the circuit cell 4B shown in FIG. 2B are laid outin the row and column directions.

Power is supplied to the circuit cells through wires typically havingthe same branch structure as that shown in FIG. 3.

In FIG. 5, only trunk lines of the branch structure are shown. To put itconcretely, in the cell layout area 1B shown in FIG. 5, hatched wiresforming a lattice shape represent trunk lines of the virtual VSS line20T and a real power-line pair (2D, 2S). In the following description,the hatched wires are referred to as a trunk-line group 2T.

The trunk-line group 2T is extended to the outside of the cell layoutarea 1B and connected to other conductive macros such as the non-appliedcircuit blocks 33 in FIG. 4 to supply power thereto. At two locations ofthe external extensions existing outside the cell layout area 1B asextensions of the trunk-line group 2T, switch blocks 2 are provided. Toput it in detail, at two locations of the row-direction externalextension, switch blocks 2 are provided and, in the same way as therow-direction external extension, at two locations of thecolumn-direction external extension, other switch blocks 2 are provided.

A diagram on the left side of FIG. 5 shows an enlarged switch block 2,in which a virtual VSS line 20T, a real VDD line 2D and areal VSS line2S are provided in the switch block 2. The real VSS line 2S and the realVDD line 2D are further extended to the outside of the switch block 2and connected to other conductive macros such as the non-applied circuitblocks 33 in the semiconductor integrated circuit shown in FIG. 4 tosupply power thereto.

The switch block 2 employs n switch transistors SWT1 to SWTn connectedin parallel between the virtual VSS line 20T and the real VSS line 2S.The gate of the switch transistor SWTm is connected to a control lineCLm where 1≦m≦n. It is to be noted that, in accordance with a controlmethod to be described later, the gates of a plurality of switchtransistors SWT may be connected to a control line CL in some cases.

The control lines CL consisting of the control lines CL1 to CLn areconnected to the switch control section 31 employed in the circuit block32 as shown in FIG. 4.

<First Basic Concept of Switch Control>

FIGS. 6A and 6B are explanatory diagrams referred to in description of afirst basic concept of switch control. As shown in FIG. 6A, a pluralityof switch transistors SWT used in the first basic concept includes aplurality of transistors having different conducting-state resistancesfrom each other. Typically, the switch transistors SWT are the switchtransistor SWT shown in FIG. 2 or the switch transistors SWT1 to SWTnshown in FIG. 5. In the typical configuration shown in FIG. 6A, theswitch transistors SWT are HR (high resistance), MR (medium resistance)and LR (low resistance) switch transistors SWT. The HR switch transistorSWT has the largest conducting-state resistance among all the switchtransistors SWT whereas the LR switch transistor SWT has the smallestconducting-state resistance among all the switch transistors SWT. The MRswitch transistor SWT has a middle conducting-state resistance betweenthe largest and smallest conducting-state resistances. However, inaccordance with the present invention, at least two switch transistorsSWT having conducting-state resistances which are different from eachother are required and four or more switch transistors SWT havingconducting-state resistances can also be used. That is to say, thenumber of types of switch transistors SWT (type represents variety ofconducting-state resistances) can be any integer as long as the integeris at least 2. In addition, the total number of transistors can be anyinteger as long as the integer is at least 2. The number of types ofswitch transistors SWT and the total number of transistors can be thesame integer; however, the number of types of switch transistors SWT isrequired be smaller than the total number of transistors. Some ofconsecutive transistors can have the uniform conducting-stateresistances.

In FIG. 6A, the source of each of the HR (high resistance) switchtransistor SWT, the MR (medium resistance) switch transistor SWT and theLR (low resistance) switch transistor SWT is connected to the commonreal VSS line 2S or the branch line 20S of the real VSS line 2S whereasthe drain of each of those switch transistors SWT is connected to thecommon virtual VSS line which is the virtual VSS line 20T shown in FIG.5 or the virtual VSS line 30S shown in FIG. 3. The gate of each of thoseswitch transistors SWT is connected through a control line CL to aswitch control section 31.

A difference in electric potential between the branch line 20S of thereal VSS line 2S as the first voltage line and the virtual VSS line 30Sas the second voltage line or a difference in electric potential betweenthe real VSS line 2S as the first voltage line and the virtual VSS line20T as the second voltage line is initially fixed and, then, from acertain point of time, the HR (high resistance) switch transistor SWT,the MR (medium resistance) switch transistor SWT and the LR (lowresistance) switch transistor SWT are put in a turned-on state at threeseparate times respectively. In this case, the changes of an electricpotential V (30S, 20T) appearing on the virtual VSS line 30S or thevirtual VSS line 20T for the three switch transistor SWT turning-onoperations are shown as three curves respectively in FIG. 6B. In thefollowing description, the electric potential is referred to as avirtual VSS-line electric potential V (30S, 20T).

As shown in FIG. 6B, the larger the conducting-state resistance, thesmaller the virtual VSS-line electric potential V (30S, 20T). That is tosay, even though there is an effect of repressing power-supply noises,the larger the conducting-state resistance, the longer the time it takesto complete an electrical discharging process.

This first basic concept carries out an operation to equalize thevoltages appearing on the first and second voltage lines through aplural times of controls to put switch transistors SWT in a conductingstate by use of, when the difference in electric potential between thefirst and second voltage lines is large, the switch transistor SWThaving a large conducting-state resistance, on the other hand, when thedifference in electric potential between the first and second voltagelines is small, the switch transistor SWT having a smallconducting-state resistance.

To put it concretely, the switch control section 31 controls atransition of each of the switch transistors SWT from a non-conductingstate to a conducting state by turning on the switch transistors SWT atseparate points of time while abiding by a rule stating: “Any specificone of the switch transistors SWT shall be put in a conducting stateonly after all the switch transistors SWT each having a conducting-stateresistance greater than the conducting-state resistance of the specificswitch transistor SWT have been put in a conducting state.”

The above rule prescribes control of an operation to change switchtransistors SWT having conducting-state resistances which are differentfrom each other from a non-conducting state to a conducting state byturning on the switch transistors SWT at separate points of time. Therule does not prescribe control of an operation to change switchtransistors SWT having conducting-state resistances which are equal toeach other from a non-conducting state to a conducting state. Thus, itis allowable to change switch transistors SWT having conducting-stateresistances which are equal to each other from a non-conducting state toa conducting state at two or more successive points of time.

For example, where the switch transistors SWT are controlled one by oneto put in a conducting state, if there are two or more switchtransistors SWT having the uniform conducting-state resistance, theswitch transistors SWT having the uniform specific conducting-stateresistance which are greater than the others can be put in a turned onstate sequentially in any arbitrary order in the uniform resistancegroup. When switch transistors SWT included in another group as theswitch transistors SWT having conducting-state resistances lower thanthe conducting-state resistance of the switch transistor SWT pertainingto the specific group is put in a turned on state, it is necessary toabide by the rule described above. That is to say, any specific one ofthe switch transistors SWT shall be put in a conducing state only afterall the switch transistors SWT each having a conducting-state resistancegreater than the conducting-state resistance of the specific switchtransistor SWT have been put in a turned on state. A typical example ofthe control will be described later.

The resistance between the first and second voltage lines is graduallyreduced by a resistance decrease every time a conduction control iscarried out to put a switch transistor SWT in a turned-on state. In thiscase, the first and second voltage lines are either the real VSS line 2Sand the virtual VSS line 20T respectively or the branch line 20S and thevirtual VSS line 30S respectively. In the course of the process toreduce the resistance, the resistance decreases may be equal to eachother for some switch conduction control operations which are carriedout consecutively. Nevertheless, in the whole process to reduce theresistance, the resistance decrease is gradually increasing.

In each of the conduction control, a current flows through the switchtransistor SWT so that the difference in electric potential between thefirst and second voltage lines decreases. Thus, in the next conductioncontrol, at least one next switch transistor SWT having aconducting-state resistance equal to (or smaller than) theconducting-state resistance of the present switch transistor SWT put ina turned-on state in the present conduction control is put in aturned-on state but the magnitude of a current flowing through the nextswitch transistor SWT is smaller than the magnitude of a current flowingthrough the present switch transistor SWT. In the whole process,however, the resistance decrease is gradually increasing. Thus, currentsflow more immediately than a case in which the resistance decrease isfixed. As a result, the high-level voltage appearing on either the firstor second voltage line immediately drops, approaching the low-levelvoltage appearing on either the second or first voltage line. This dropis obvious from the fact that the use of a switch transistor SWT havinga small conducting-state resistance reduces the length of time forcompleting discharge as shown in FIG. 6B.

Each of the HR (high resistance) switch transistor SWT, the MR (mediumresistance) switch transistor SWT and the LR (low resistance) switchtransistor SWT which are shown in FIG. 6A can be a single transistor ora set of a plurality of unit transistors. If each of those switchtransistors SWT is a set of a plurality of unit transistors, the unittransistors included in any one of the switch transistors SWT arecontrolled simultaneously to enter a turned-on or turned-off state atthe same time. For this reason, the unit transistors composing any oneof the switch transistors SWT can be conceptually regarded as onetransistor.

If the unit transistors have a uniform conducting-state resistance, thehigh, middle or low conducting-state resistance of a switch transistorSWT is determined by the number of unit transistors composing the switchtransistor SWT. To be more specific, the higher the number of unittransistors included in a switch transistor SWT as unit transistors tobe controlled simultaneously to enter a turned-on or turned-off state,the lower the conducting-state resistance. It is to be noted, however,that also in this case, it is necessary to abide by the rule describedabove and it is allowable to configure any specific one of switchtransistors SWT to include as many unit transistors as unit transistorscomposing a switch transistor SWT to be put in a turned-on stateimmediately before or after the specific switch transistor SWT.

A typical configuration including switch transistors SWT each having aplurality of unit transistors to serve as one of the switch transistorsSWT shown in FIG. 6A will be described later in detail.

<Second Basic Concept of Switch Control>

FIGS. 7A and 7B are explanatory diagrams of a second basic concept ofswitch control.

As shown in FIG. 7A, a plurality of switch transistors SWT have auniform conducting-state resistance and are to be put in a conductingstate at gradually shorter switch turning-on time intervals in the wholeswitch conduction control to reduce the resistance between the first andsecond voltage lines in accordance with the second basic concept.Typically, the switch transistors SWT are the switch transistor SWTshown in the diagrams of FIG. 2 or the switch transistors SWT1 to SWTnshown in the diagram of FIG. 5. The phrase stating: “gradually shortertime intervals in the whole process” also has an implication that two ormore consecutive intervals at which switch transistors SWT are put in aturned-on state have lengths equal to each other. However, it meansthat, at least, the switch turning-on time interval between the firstand next switch transistors SWT shall be longer than the switchturning-on time interval between the last and immediately before thelast switch transistors SWT. In other words, the switch conductioncontrol based on the second basic concept is characterized in that theswitch control section 31 executes switch conduction control to carryout switch conduction control operations to sequentially put a pluralityof switch transistors SWT in a turned-on state at a plurality of switchturning-on time intervals including at least an earlier switchturning-on time interval and a later switch turning-on time intervalwith a length shorter than the length of the earlier switch turning-ontime interval.

In the case of the diagram of FIG. 7A, only the switch transistors SWT1to SWT3 are shown. It is to be noted, however, the present invention isnot limited to this configuration. That is to say, the number of switchtransistors SWT can be any integer as long as the integer is at leastequal to 2.

FIG. 7B shows a relation between the change of the virtual VSS-lineelectric potential V (30S, 20T) and the lapse of time. In FIG. 7B, asolid line represents the case in which the number of switch transistorsSWT is 3 whereas a dashed line represents the case in which the numberof switch transistors SWT is 4.

In the case in which the number of switch transistors SWT is 3, a switchturning-on time interval T23 between an operation to put the switchtransistor SWT2 in a turned-on state and an operation to put the switchtransistor SWT3 in a turned-on state is deliberately made shorter than aswitch turning-on time interval T12 between an operation to put theswitch transistor SWT1 in a turned-on state and an operation to put theswitch transistor SWT2 in a turned-on state.

In the same way as the case in which the number of switch transistorsSWT is 3, in the case in which the number of switch transistors SWT is4, the switch turning-on time interval between consecutive operations toput switch transistors SWT can be sequentially made shorter. In thetypical case represented by the dashed line shown in FIG. 7B, however,the switch turning-on time interval T23 between an operation to put theswitch transistor SWT2 in a turned-on state and an operation to put theswitch transistor SWT3 in a turned-on state is made equal to the switchturning-on time interval T12 between an operation to put the switchtransistor SWT1 in a turned-on state and an operation to put the switchtransistor SWT2 in a turned-on state whereas a switch turning-on timeinterval T34 between an operation to put the switch transistor SWT3 in aturned-on state and an operation to put the switch transistor SWT4 in aturned-on state is made shorter than the switch turning-on time intervalT12 which is equal to the switch turning-on time interval T23.

In an initial state of the conduction control, the difference inelectric potential between the first and second voltage lines is large.In this case, the first and second voltage lines are either the real VSSline 2S and the virtual VSS line 20T respectively or the branch line 20Sand the virtual VSS line 30S respectively. In this initial state, ittakes time to stabilize the difference in electric potential between thefirst and second voltage lines from a state of instability generated atthe start of the switch conduction control. Thus, in accordance with thesecond basic concept, in this initial state, the switch turning-on timeinterval is deliberately made long. When another switch transistor SWTis put in a turned-on state after the first switch transistor SWT hasbeen once put in a turned-on state, on the other hand, the time it takesto stabilize the difference in electric potential between the first andsecond voltage lines is relatively short because the totalconducting-state resistance between the first and second voltage lineshas become smaller.

In accordance with the second basic concept paying attention to the factthat the time it takes to stabilize the difference in electric potentialbetween the first and second voltage lines is becomes short as describedabove, the switch control section 31 executes conduction control tosequentially put a plurality switch transistors SWT in a turned-on stateat a plurality of switch turning-on time intervals including at least anearlier switch turning-on time interval and a later switch turning-ontime interval with a length shorter than the length of the earlierswitch turning-on time interval.

In the case of this embodiment, however, the switch control section 31needs only to execute switch conduction control to sequentially put aplurality switch transistors SWT in a turned-on state at a plurality ofswitch turning-on time intervals including at least an earlier switchturning-on time interval and a later switch turning-on time intervalwith a length shorter than the length of the earlier switch turning-ontime interval. The switch control section 31 is by no means required towait for the difference in electric potential to get stabilized prior toexecution of each of the switch conduction control operations.Nevertheless, it is desirable to set a prerequisite requiring that theswitch control section 31 shall wait for the difference in electricpotential to get stabilized prior to execution of each of the switchconduction control operations. This is because, by setting such aprerequisite, it is easy to estimate an electric potential appearing ata switch-on time and, hence, it is easy to design the plurality ofswitch conduction control. Nevertheless, the present invention is notrestricted by the prerequisite.

As explained above, in an initial state of the conduction control, thedifference in electric potential between the first and second voltagelines is large. Thus, in accordance with the first and second basicconcepts described above, only some of a plurality of switch transistorsSWT are each put in a turned-on state in the initial state. As a result,the resistance between the first and second voltage lines does not dropabruptly so that the maximum value of the magnitude of a current flowingthrough the first voltage line is small. As a result, it is possible torepress the peak of variations of a voltage appearing on the firstvoltage line. In addition, in comparison with control to sequentiallyput switch transistors SWT having a uniform conducting-state resistanceat equal switch turning-on time intervals, the fast voltage equalizationprocess described above reduces the length of time it takes to completethe conduction control operations which are commenced at the start ofthe switch conduction control.

The first and second basic concepts described above can be adoptedseparately from each other or applied at the same time as a combinationof methods.

<Typical Switch Control>

The following description explains typical concrete control as anexample of applying the first and second basic concepts at the sametime.

FIG. 8 is an explanatory diagram referred to in description of a typicalexample of the switch control.

The technical term ‘system’ used in the following description of thetypical concrete control with reference to the diagram of FIG. 8 means asingle switch transistor SWT or a group of switch transistors SWT. Thesingle switch transistor SWT included in a system or the switchtransistors SWT included in a system are put in a turned-on state at thesame time. Much like the diagram of FIG. 6A, in the diagram of FIG. 8,each HR (high resistance) switch transistor SWT is shown as a transistorcircuit-symbol with a black channel, each MR (medium resistance) switchtransistor SWT is shown as a transistor circuit-symbol with a hatchedchannel whereas each LR (low resistance) switch transistor SWT is shownas a transistor circuit-symbol with a channel like a line segment, thatis, a transistor circuit-symbol with neither black channel nor hatchedchannel.

In the diagram of FIG. 8, each of the first to mth systems is an HR(high resistance) switch transistor SWT whereas the (m+1)th system is anMR (medium resistance) switch transistor SWT. Each of the (m+2)th to nthsystems is an LR (low resistance) switch transistor SWT. It is to benoted that the configuration of the systems can be changed arbitrarilyto a different configuration reflecting other system counts eachrepresenting the number of systems each including switch transistors SWThaving a uniform conducting-state resistance. For example, it ispossible to provide a system configuration in which, conversely, aplurality of systems each include an MR (medium resistance) switchtransistor SWT whereas only one system includes an HR (high resistance)switch transistor SWT and only one system includes an LR (lowresistance) switch transistor SWT.

Numbers each assigned to a system starts with 1 and, the larger thenumber assigned to a system, the later the operation carried out to puta switch transistor SWT included in the system, to which the number isassigned, in turned-on state. The switch control section 31 isconfigured to include hardware, software or both hardware and softwareas means capable of executing a sequence of operations to sequentiallyactivate control lines CL connected to the systems in order to put theswitch transistors SWT included in the systems in a turned-on state insystem units.

As a technique for setting the conducting-state resistance of a switchtransistor SWT, it is possible to adopt a technique for setting thechannel concentration of the transistor SWT in a manufacturing processof the transistor. In this embodiment, however, the gate width of aswitch transistor SWT is determined in a manufacturing process of thetransistor SWT in order to set the conducting-state resistance of thetransistor SWT.

The larger the gate width of a switch transistor SWT, the smaller theconducting-state resistance of the transistor SWT. In the work ofdesigning a switch transistor SWT as a cell including unit transistorsconnected to each other in parallel, it is desirable to adopt a methodfor setting the effective gate width of the cell by determining thenumber of aforementioned unit transistors each used as a basic unithaving a small gate width.

If the desirable method described above is adopted, for example, an HR(high resistance) switch transistor SWT does not have to be a singleswitch transistor SWT having a conducting-state resistance determined inadvance. Instead, the HR (high resistance) switch transistor SWT can bea switch transistor cell including a plurality of unit transistorsconnected to each other in parallel and a process to set theconducting-state resistance of the HR (high resistance) switchtransistor SWT can be controlled in detail by determining the number ofaforementioned unit transistors. Of course, it is also possible toassign a conducting-state resistance determined in advance to each ofthe HR (high resistance) switch transistor SWT, the MR (mediumresistance) switch transistor SWT and the LR (low resistance) switchtransistor SWT.

Without regard to whether a switch transistor SWT composing each of thefirst to nth systems shown in FIG. 8 is a single switch transistor SWTor a switch transistor cell employing a plurality of unit transistors,in the entire configuration, the larger the number assigned to aparticular system, the larger the decrease of the conducting-stateresistance. In a group of systems including switch transistors SWThaving a uniform conducting-state resistance, the consecutive equaldecreases of the conducting-state resistance is allowed.

With the scheme described above, in the entire configuration, the largerthe number assigned to a system, the larger the voltage drop obtained asa result of applying the same voltage between the source and drain ofthe switch transistor SWT in each of the systems for the same period oftime.

FIGS. 9A and 9B are diagrams showing curves each representing a relationbetween a voltage appearing on a virtual VSS line 30S or a virtual VSSline 20T and the lapse of time as a result of conduction controlexecuted by the switch control section 31 and showing timing charts.FIG. 9A is a diagram showing timings with which systems are activated.FIG. 9B shows the diagram in FIG. 9A, which is redrawn by focusing onthe lapse of time indicating switch turning-on time intervals.

The switch control section 31 executes switch control as shown in FIGS.9A and 9B in an initial state in order to drive the MTCMOS circuit block1, which is shown in the diagrams of FIGS. 1 to 5 to serve as thesubject of control, to recover from a power-supply cut-off state.

To put it concretely, in accordance with a recovery command issued by asection such as a CPU, first of all, the switch control section 31activates a control line CL connected to the first system in order toput an HR (high resistance) switch transistor SWT pertaining to thefirst system in a turned-on state. This is because the HR (highresistance) switch transistor SWT pertaining to the first system has alarge conducting-state resistance and, by putting the HR (highresistance) switch transistor SWT in a turned-on state, power-supplynoises can be repressed.

A state prior to a first conduction control is a power-supply cut-offstate and, if the power-supply cut-off state lasts long, the virtual VSSline 30S or the virtual VSS line 20T is electrically charged with alarge leak current flowing through a circuit cell employing a transistorhaving a small threshold voltage. Thus, an electric potential appearingon the virtual VSS line 30S or the virtual VSS line 20T increases to alevel close to the power-supply voltage VDD as shown in FIGS. 9A and 9B.

In this state, when the first switch conduction control operation iscarried out, the electric potential appearing on the virtual VSS line30S or the virtual VSS line 20T decreases by a voltage drop. The firstswitch conduction control operation is an operation started with atiming denoted by reference phrase ‘First system’ in FIG. 9A. Thevoltage drop is largest among all voltage drops due to a large voltageapplied between the source and gain electrodes of the HR (highresistance) switch transistor SWT pertaining to the first system. Sincethe conducting-state resistance of the HR (high resistance) switchtransistor SWT is also relatively large, however, a sharp voltage dropis repressed. Thus, power-supply noises can also be repressedeffectively. With the lapse of time, the electric potential appearing onthe virtual VSS line 30S or the virtual VSS line 20T is converged to afixed level determined by the large conducting-state resistance of theHR (high resistance) switch transistor SWT pertaining to the firstsystem.

As the electric potential appearing on the virtual VSS line 30S or thevirtual VSS line 20T has been settled at the fixed level, next, thesecond system including a HR (high resistance) switch transistor SWThaving a conducting-state resistance equal to or slightly smaller thanthe conducting-state resistance of the HR (high resistance) switchtransistor SWT included in the first system is activated by carrying outa second switch conduction control operation. The second switchconduction control operation is an operation started with a timingdenoted by reference phrase ‘Second system’ in the model diagram of FIG.9A. In the second conduction control, the voltage applied between thesource and gain of the HR (high resistance) switch transistor SWTpertaining to the second system prior to the second switch conductioncontrol operation is low in comparison with the voltage applied betweenthe source and gain electrodes of the HR (high resistance) switchtransistor SWT pertaining to the first system prior to the first switchconduction control operation. Thus, even though the HR (high resistance)switch transistor SWT pertaining to the second system has aconducting-state resistance slightly smaller than the conducting-stateresistance of the HR (high resistance) switch transistor SWT pertainingto the first system, the voltage drop occurring in the second switchconduction control operation can be repressed to a voltage decreasesmaller than that of the first switch conduction control operation. As aresult, power-supply noises generated in the second switch conductioncontrol operation can also be repressed effectively.

Thereafter, a switch conduction control operation is carried out on eachof the third to mth systems each including an HR (high-resistance)switch transistor SWT having a large conducting-state resistance in thesame way as the first and second systems.

Then, a control line CL connected to an MR (medium resistance) switchtransistor SWT pertaining to the (m+1)th system is activated. The(m+1)th conduction control operation starts with a timing denoted byreference phrase ‘(m+1)th system’ in FIG. 9A.

Subsequently, a control line CL connected to an LR (low resistance)switch transistor SWT pertaining to the (m+2)th system is activated. The(m+2)th conduction control starts with a timing denoted by referencephrase ‘(m+2)th system’ in FIG. 9A.

Thereafter, the operation to activate a control line CL is carried outrepeatedly in the same way as the systems described so far till the nthswitch conduction control operation is carried out on the last nthsystem.

As shown in FIG. 9A, by carrying out a sequence of conduction controloperations with a plurality of different timings each assigned to one ofthe operations in the way explained above, it is possible to executecontrol for gradually reducing the magnitude of the voltage dropdescribed above. Thus, power-supply noises that would otherwise remainafter the first switch conduction control operation carried out on thefirst system no longer appear in the subsequent switch conductioncontrol operations each carried out on one of the remaining systems. Theconducting-state resistance of the HR (high resistance) switchtransistor SWT pertaining the first system is set at a value thatprevents the peak of power-supply noises generated during the firstswitch conduction control operation from exceeding a referencedetermined in advance. It is thus possible to effectively preventgeneration of power-supply noises affecting delay characteristicsthrough the real VSS line 2S for a non-MTCMOS applied circuit cellincluded in the same circuit block or another circuit block.

By way of experiment, it is assumed that the switch turning-on timeinterval between the start of a switch conduction control operationcarried out on any particular system and the start of a switchconduction control operation carried out on a system activated after theparticular system is made uniform for any two consecutive systems. Evenfor such a configuration, in accordance with this embodiment, as awhole, switch transistors SWT each used in a system are sequentiallyselected and put in a turned-on state in an order starting with a switchtransistor SWT having the largest conducting-state resistance among theswitch transistors SWT and continuing sequentially to switch transistorsSWT each having a conducting-state resistance smaller than theconducting-state resistance of a switch transistor SWT selected and putin a turned-on state immediately before so that it is possible to reducethe length of time it takes to complete a sequence of switch conductioncontrol operations which are commenced at the start of the switchconduction control in comparison with a configuration employing onlyswitch transistors SWT each having a large conducting-state resistancefor repressing the peak of power-supply noises generated initially.

In order to further reduce the length of time, the control is executedto gradually reduce the switch turning-on time interval as a whole, asshown in FIG. 9B.

To put it concretely, the switch turning-on time intervals T between thestarts of the systems satisfy the inequality expression T1≧T2≧ . . .≧Tm≧Tm+1≧Tm+2≧ . . . ≧Tn−1 where reference notation Ti denotes theswitch turning-on time interval between the starts of the ith system andthe (i+1)th system. The inequality expression indicates that the switchturning-on time interval Ti+1 may be set at a value equal to the switchturning-on time interval Ti. Nevertheless, the switch turning-on timeinterval Ti is gradually reduced with the lapse of time over the entireperiod of the switch conduction control. Even though an inequality sign≧ in the inequality expression may be replaced with the equality sign =;however, it is not allowed to replace each of the inequality signs ≧ inthe inequality expression with the equality sign =.

Thus, it is possible to reduce the length of time it takes to complete asequence of switch conduction control operations which are commenced atthe start of the switch conduction control in comparison with aconfiguration in which the switch turning-on time intervals between thestarts of the systems are deliberately made uniform.

FIG. 9C is a waveform diagram showing timing charts of the controlsignals CL each connected to one of the systems.

FIG. 10 is an explanatory diagram showing a configuration which isdesigned so that, the larger the number assigned to a system, the largerthe number of unit transistors. By increasing the number of unittransistors, the conducting-state resistance of the switch transistorSWT for the system can be decreased finely.

If the number of systems increases, the number of control signals CLrises. With the raised number of control signals CL, however, the largercontrol-signal arrangement space occupied by the control signals CL maybe the main cause of the increased area in some cases. In order toreduce the number of systems without decreasing the number of differentvalues assigned to the conducting-state resistance, it can adopt atechnique whereby each of the systems is configured by connecting unittransistors in parallel and increase the number of unit transistorsincluded in a system with the number assigned to the system as shown inthe explanatory diagram of FIG. 10.

If a space is wasted due to variations of the unit-transistor count fromsystem to system, the switch transistors SWT are arranged to form amatrix in place of an array shown in the diagrams of FIGS. 5, 6A and 7A.Then, switch transistors SWT in each system shown in the explanatorydiagram are connected to each other by making use of wires throughadoption of the branch structure as shown in FIG. 10.

Each of the embodiments described above executes conduction control onswitch transistors SWT connected in parallel between a first voltageline which can be the real VSS line 2S and a second voltage line whichcan be the virtual VSS line 30S or the virtual VSS line 20T, graduallyincreasing the number of aforementioned switch transistors SWT each putin a conductive state. Thus, each of the embodiments offers a merit thatit is possible to reduce the length of time it takes to complete asequence of conduction controls which are commenced at the start of theconduction control while repressing the peak of variations of a voltageappearing on the first voltage line, that is, repressing the peak ofpower-supply noises.

In addition, it should be understood by those skilled in the art that avariety of modifications, combinations, sub-combinations and alterationsmay occur, depending on design requirements and other factors as far asthey are within the scope of the appended claims or the equivalentsthereof.

What is claimed is:
 1. A semiconductor integrated circuit comprising: afirst voltage line on which a specific one of a power-supply voltage anda reference voltage appears; a second voltage line; a plurality ofcircuit cells each receiving power generated as a difference between avoltage appearing on said second voltage line and the other one of saidpower-supply voltage and said reference voltage; a plurality of switchtransistors connected in parallel between said first and second voltagelines to serve as switch transistors including switch transistors havingconducting-state resistances which are different from each other; and aswitch conduction control section configured to control a transition ofeach of said switch transistors from a non-conducting state to aconducting state at separate points of time while abiding by a rulestating: any specific one of said switch transistors shall be put in aconducting state only after all said switch transistors each having aconducting-state resistance greater than the conducting-state resistanceof said specific switch transistor have been put in a conducting state.2. The semiconductor integrated circuit according to claim 1 whereineach of said switch transistors employs a plurality of unit transistorswhich are controlled by said switch conduction control section to beturned on or turned off at the same time and have a uniformconducting-state resistance.
 3. The semiconductor integrated circuitaccording to claim 1 wherein, when controlling a transition of each ofsaid switch transistors from a non-conducting state to a conductingstate at separate points of time, said switch conduction control sectionfixes the number of said switch transistors to be controlled at the samepoint of time for each of said points of time.
 4. The semiconductorintegrated circuit according to claim 1 wherein, when controlling atransition of each of said switch transistors from a non-conductingstate to a conducting state at separate points of time, said switchconduction control section gradually increases the number of said switchtransistors to be controlled at the same point of time.
 5. Thesemiconductor integrated circuit according to claim 1 wherein, whencontrolling a transition of each of said switch transistors from anon-conducting state to a conducting state at separate points of time,said switch conduction control section gradually decreases timeintervals of conduction controls.
 6. A semiconductor integrated circuitcomprising: a first voltage line on which one of a power-supply voltageand a reference voltage appears; a second voltage line; a plurality ofcircuit cells each receiving power generated as a difference between avoltage appearing on said second voltage line and the other one of saidpower-supply voltage and said reference voltage; a plurality of switchtransistors connected in parallel between said first and second voltagelines; and a switch conduction control section configured to control atransition of each of said switch transistors from a non-conductingstate to a conducting state by turning on said switch transistors at aplurality of time intervals, each time interval of said plurality oftime intervals beginning with a turning on of one of said switchtransistors and ending with a turning on of a subsequent othertransistor of said switch transistors, wherein the plurality of timeintervals includes a specific time interval that is shorter than apreceding time interval.
 7. A power-supply control method to be adoptedby a semiconductor integrated circuit including: a first voltage line onwhich a specific one of a power-supply voltage and a reference voltageappears; a second voltage line; a plurality of switch transistorsconnected in parallel between said first and second voltage lines toserve as switch transistors including switch transistors havingconducting-state resistances which are different from each other; and aplurality of circuit cells each receiving power generated as adifference between a voltage appearing on said second voltage line andthe other one of said power-supply voltage and said reference voltage,said power-supply control method comprising the step of controlling anoperation to supply power to said circuit cells by putting each of saidswitch transistors in a turned-off state or a turned-on state, through aconduction control of a transition of each of said switch transistorsfrom a non-conducting state to a conducting state at separate points oftime while abiding by a rule stating: any specific one of said switchtransistors shall be put in a conducting state only after all saidswitch transistors each having a conducting-state resistance greaterthan said conducting-state resistance of said specific switch transistorhave been put in a conducting state.
 8. The power-supply control methodto be adopted by a semiconductor integrated circuit, according to claim7, wherein each of said switch transistors is configured to include aplurality of unit transistors having uniform conducting-stateresistances, controlled through the conduction control to be turned offand turned on at the same point of time; and during the conductioncontrol, the number of said unit transistors to be controlledsimultaneously at the same point of time is made gradually greater.
 9. Asemiconductor integrated circuit comprising: a first voltage lineincluding one of a power-supply voltage and a reference voltage; asecond voltage line; a plurality of circuit cells each receiving powergenerated as a difference between a voltage included in said secondvoltage line and the other one of said power-supply voltage and saidreference voltage; a plurality of switch transistors connected inparallel between said first and second voltage lines to serve as switchtransistors, the plurality of switch transistors including switchtransistors having conducting-state resistances that are different fromeach other; and a switch conduction control section configured tocontrol a transition of each of said switch transistors from anon-conducting state to a conducting state at separate points of time,wherein a switch transistor of said plurality of switch transistors isput in a conducting state only after other switch transistors of saidplurality of switch transistors having a conducting-state resistancegreater than the conducting-state resistance of the switch transistorhave been put in a conducting state.
 10. The semiconductor integratedcircuit according to claim 9, wherein each of said switch transistorsemploys a plurality of unit transistors that are controlled by saidswitch conduction control section to be turned on or turned off at thesame time and have a uniform conducting-state resistance.
 11. Thesemiconductor integrated circuit according to claim 9, wherein, whencontrolling a transition of each of said switch transistors from anon-conducting state to a conducting state at separate points of time,said switch conduction control section fixes the number of said switchtransistors to be controlled at the same point of time for each of saidpoints of time.
 12. The semiconductor integrated circuit according toclaim 9, wherein, when controlling a transition of each of said switchtransistors from a non-conducting state to a conducting state atseparate points of time, said switch conduction control sectiongradually increases the number of said switch transistors to becontrolled at the same point of time.
 13. The semiconductor integratedcircuit according to claim 9, wherein, when controlling a transition ofeach of said switch transistors from a non-conducting state to aconducting state at separate points of time, said switch conductioncontrol section gradually decreases time intervals of conductioncontrols.
 14. A semiconductor integrated circuit comprising: a firstswitch transistor connected between a first voltage line and a secondvoltage line, the first switch transistor having a firstconducting-state resistance; a second switch transistor connectedbetween the first voltage line and the second voltage line, the secondswitch transistor having a second conducting-state resistance; a thirdswitch transistor connected between the first voltage line and thesecond voltage line, the third switch transistor having a thirdconducting-state resistance, wherein the first conducting-stateresistance differs from the second conducting-state resistance, thethird conducting-state resistance differing from the firstconducting-state resistance.
 15. The semiconductor integrated circuitaccording to claim 14, wherein the first voltage line extends along adirection, this second voltage line extending along the direction. 16.The semiconductor integrated circuit according to claim 14, wherein thesecond switch transistor is between the first switch transistor and thethird switch transistor.
 17. The semiconductor integrated circuitaccording to claim 14, further comprising: a circuit cell connectedbetween the second voltage line and a third voltage line, the secondvoltage line and the third voltage line being connected to the circuitcell.
 18. The semiconductor integrated circuit according to claim 14,further comprising: a switch conduction control section configured tocontrol a transition of the first switch transistor from anon-conducting state to a conducting state, the transition of the firstswitch transistor establishing a first electrical connection between thefirst voltage line and the second voltage line.
 19. The semiconductorintegrated circuit according to claim 18, wherein the switch conductioncontrol section is configured to control a transition of the secondswitch transistor from the non-conducting state to the conducting state,the transition of the second switch transistor establishing a secondelectrical connection between the first voltage line and the secondvoltage line.
 20. The semiconductor integrated circuit according toclaim 19, wherein the switch conduction control section is configured tocontrol a transition of the third switch transistor from thenon-conducting state to the conducting state, the transition of thethird switch transistor establishing a third electrical connectionbetween the first voltage line and the second voltage line.
 21. Thesemiconductor integrated circuit according to claim 14, wherein thesecond conducting-state resistance differs from the thirdconducting-state resistance.
 22. The semiconductor integrated circuitaccording to claim 14, wherein the first conducting-state resistance ishigher than the second conducting-state resistance.
 23. Thesemiconductor integrated circuit according to claim 14, wherein thefirst conducting-state resistance is higher than the thirdconducting-state resistance.
 24. The semiconductor integrated circuitaccording to claim 14, wherein the second conducting-state resistance ishigher than the third conducting-state resistance.
 25. The semiconductorintegrated circuit according to claim 14, wherein a gate width of thethird switch transistor is larger than a gate width of the first switchtransistor.
 26. The semiconductor integrated circuit according to claim25, wherein the gate width of the third switch transistor is larger thana gate width of the second switch transistor.
 27. The semiconductorintegrated circuit according to claim 26, wherein the gate width of thesecond switch transistor is larger than a gate width of the first switchtransistor.